1. Field of the Invention
The present invention generally relates to integrated circuit memory devices and, more particularly, to memory devices that require refresh operations to maintain data, such as dynamic random access memory (DRAM) devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for dynamic random access memory (DRAM) devices. A DRAM device is generally a volatile memory device where each memory cell consists of one transistor and one capacitor. Such memory cells require periodic refreshing to protect the data stored in a memory cell from corruption or decaying over time. Refreshing the memory cells is a power-consuming operation. In battery-powered computer systems (e.g., palm-top computers, hand-held electronic devices, and the like), minimization of power consumption is critically important in prolonging battery life.
In advanced DRAM devices, during a refresh operation, power consumption may be reduced by recycling a portion of bit line charges of bit line sense amplifiers (BLSAs) involved in a refresh operation in a subsequent refresh operation. As used herein, the term recycling generally refers to transferring (or sharing) bit line charges from one array of BLSAs involved in a refresh operation to another array of BLSAs to be involved in a subsequent refresh operation. However, according to conventional recycling techniques, the remaining portions of bit line charges are not utilized, as described below in reference to FIGS. 1-4.
FIG. 1 depicts a block diagram of a DRAM device 100. The DRAM device 100 generally comprises a system controller 102, a memory 104, an address bus 120, a command (i.e., system) bus 122, and a data bus 116. The system controller 102 may be further coupled to a processor 124 of an external electronic device (e.g., portable computer, cell phone, and the like) using, for example, an application-specific interface 112.
The memory 104 generally includes one or more component memories 104K and a block 118 of data input/output buffers and multiplexers. Component memories and their functional devices are identified herein using the same reference numerals, except that the suffix “K”, where K is an integer from 1 to N, has been added to differentiate between the individual memories and devices. Illustratively, a component memory 104K comprises an address decoder 106K, a memory bank 108K, a sense amplifier array 110K, a refresh controller 112K, and a bank controller 114K.
FIG. 2 depicts a portion of a circuit configuration of the component memory 104K. The memory bank 108K generally comprises at least one plurality of arrays of memory cells 200 and at least one a plurality of paired bit lines 202B and complimentary bit lines 204B, where B is an integer from 1 to M. The memory cells 200 are selectively coupled to the lines 202B and 204B. In the sense amplifier array 110K, the lines 202B and 204B are cross-coupled to respective bit line sense amplifiers (BLSA) 206B. Each BLSA 206B comprises power nodes 214S and 216S that are selectively coupled to a pre-charge circuit 224K of the refresh controller 112K using corresponding power lines of a pre-charging bus 218K and switches 212B. To transfer a charge from one BLSA (e.g., BLSA 206B) to another BLSA (e.g., BLSA 206B+1), the BLSA 206B and BLSA 206B+1 are selectively interconnected using switches 210 (e.g., switches 2101−M). The switches 210 and 212 are selectively controlled by the sensing controller 222K of the refresh controller 112K using corresponding control lines 211 and 213 of a control bus 208K.
FIG. 3 depicts a block diagram of an exemplary circuit configuration 300 for use in recycling. In FIG. 3, for a purpose of graphical clarity, components of the pre-charge circuits (i.e., switches 212B, control lines 213B, and corresponding power lines between the BLSA 206B and pre-charging bus 218K) are not shown. Conventionally, during the refresh operation in the component memory 104K, pre-selected pluralities (i.e., arrays) of the BLSAs 206B, memory arrays 220B, and switches 210S are operated at the same time (i.e., synchronically).
Operation of components of the circuit configuration 300 may best be described with reference to FIG. 4, which depicts a flow chart of exemplary operations 400 for refreshing memory arrays 220, utilizing conventional recycling techniques. In other words, to best understand the operations 400, the reader should simultaneously refer to FIGS. 3 and 4.
The operations 400 begin at step 402 and proceed to performing an array refresh operation 404, including steps 406-412. At step 406, the refresh controller 112K via the pre-charging bus 218K activates the BLSA array 206B. During step 406, the pre-charge circuit 224K selectively applies a pre-charge voltage to the power nodes 214B and 216B of the BLSA array 206B using the power lines of the pre-charging bus 218 and switches 212B. At step 408, memory cells 200 of the array 220B are refreshed using a conventional routine. Such a routine generally comprises sensing a content of a memory cell and charging a cell capacitor to the full respective logic level (i.e., a full logic high or logic low) using the BLSA array 206B.
At step 410, charge is transferred (e.g., recycled) from the BLSA array 220B to the array 220B+1. For example, the sensing 222 may momentarily close the switches 2101 to transfer a portion of the charge from the BLSA array 206M to the BLSA array 2062. Similarly, switch 210S may be closed to recycle charge from the BLSA array 206M−1 to the BLSA array 206M. At step 412, having already recycled charge from the BLSA array 206B, power lines of the BLSA array 206B are equalized. If all arrays 220B of the memory 104K have been not been refreshed (as determined at step 414), the next array to be refreshed array 220B+1 is selected (step 416) and the cycle 404 is performed for the arrays 220B+1. Such cycles 404 continue until all memory arrays of the memory device are refreshed.
In preparation of sensing operations, BLSA arrays are typically precharged to a level about half the voltage of a bit line high (VBLH). Due to charge sharing during recycling, power lines of the recipient array (e.g, BLSA array 206B+1) are additionally charged to a level about halfway between this pre-charge level and the final value of the source array (e.g. BLSA array 206B). As such, the charge required to bring the power lines of the BLSA array 206B+1 (from the precharge level) to a full level for sensing may be reduced by approximately 50%, which represents a substantial power savings.
However, during equalization (at step 412), the remaining charge of the BLSA array 206B, is lost without any useful utilization. Power losses caused by low efficiency of such one-time recycling of charge during refresh operations may substantially limit the amount of power savings achievable by recycling, thus shortening operational interval of battery-powered systems that use DRAM devices, as well as degrade the thermal budget of these memory devices.
Accordingly, there is a need in the art for an improved method and circuit configuration for multiple recycling of bit line charges.